Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor device having damascene wires.
Description of Related Art
With the recent integration of a semiconductor device, refinement of wires is required. In order to satisfy this requirement, employment of copper (Cu) wires or the like having small electrical resistance in place of conventional aluminum (Al) wires or the like is studied.
The damascene process is known as a method of forming fine copper wires.
In the damascene process, a first insulating layer is first laminated on a semiconductor substrate. Then, a first wiring trench is formed in a prescribed wire-forming region of the first insulating layer. Then, a copper film filling up the first wiring trench is formed on the first insulating layer. Then, the copper film is polished by chemical mechanical polishing (CMP) for removing excess copper not embedded in the first wiring trench, thereby forming a first copper wire embedded in the first wiring trench. Thereafter a second insulating is laminated on the first insulating layer, and a via hole reaching the first copper wire is formed in the second insulating layer. Further, a third insulating layer is laminated on the second insulating layer formed with the via hole. Then, a second wiring trench communicating with the via hole is formed in a prescribed wire-forming region of the third insulating layer. A copper film is formed on the third insulating layer, embedded in the second wiring trench and polished by CMP, thereby forming a second copper wire electrically connected with the first copper wire through the via hole.
In the polishing by CMP (hereinafter simply referred to as “CMP treatment”), however, the polishing rates for the copper films and the insulating layers are different from each other. When the insulating layers are dispersed in wiring density, therefore, the surfaces of the copper wires and the insulating layers are partially not planarized, but easily indented by the so-called dishing. Particularly when a multilevel interconnection structure is formed by laminating a plurality of insulating layers, such dishing is caused in the respective insulating layers, leading to remarkable indentations on the surfaces of copper wires and the insulating layers in upper layers. This may result in various inconveniences such as dispersion in wiring resistance, defective resolution in photolithography and a short circuit between the respective wires. Such inconveniences cause reduction of the yield in the manufacturing steps and reduction of the reliability in quality of the semiconductor device.
Therefore, a technique has been proposed to embed dummy wires not electrically connected with the copper wires in the respective insulating layers on non-wire-forming regions other than the wire-forming regions formed with the copper wires (refer to Japanese Unexamined Patent Publication No. 2004-153015, for example). Thus, apparent wiring density in the respective insulating layers can be made uniform, and dishing can be suppressed in the CMP treatment.
In the structure according to the above-mentioned proposal, however, the non-wire-forming regions of the respective layers are set to completely coincide with one another in plan view. Even if any of the wire-forming regions includes a portion provided with no wire, no dummy wire is formed on this portion. Therefore, a layer still dispersed in wiring density may remain to be dished out by the CMP treatment.
In general, a bonding pad made of a metal is laminated on the surface of a semiconductor device for electrically connecting the semiconductor device with an external device. A plurality of wiring layers having wiring patterns are laminated under the bonding pad. The wiring patterns of the respective wiring layers are electrically connected with one another through connecting vias. The wiring pattern of the uppermost wiring layer is electrically connected with the bonding pad through the corresponding connecting via. The wiring pattern of the uppermost wiring layer is further electrically connected with an element built on a semiconductor substrate for the semiconductor device. The bonding pad and a lead electrode (external electrode) of a lead frame are connected with each other by a bonding wire formed by a gold thin wire, thereby attaining electrical connection between the semiconductor device (element built on the semiconductor substrate) and the lead frame.
According to another method employing the damascene process, a first via hole reaching a semiconductor substrate is first formed in a first insulating layer made of silicon oxide (SiO2) formed on the semiconductor substrate. Then, a first wiring trench is formed in the first insulating layer formed with the first via hole. Thereafter, a copper film is formed on the first insulating layer to fill up the first via hole and the first wiring trench. Then, the copper film is polished by chemical mechanical polishing (CMP) for removing excess copper not embedded in the first wiring trench, thereby forming a first copper wire embedded in the first wiring trench.
Then, a second insulating layer is formed on the first insulating layer, and a second via hole reaching the first copper wire is formed in the second insulating layer. A second wiring trench corresponding to the pattern of a bonding pad is formed in the second insulating layer formed with the second via hole, and copper is embedded in the second via hole and the second wiring trench, thereby forming a second copper wire electrically connected with the first copper wire.
Further, a third insulating layer is formed on the second insulating layer, and a third via hole reaching the second copper wire is formed in the third insulating layer. A pad trench for embedding the bonding pad is formed in the third insulating layer, and copper is embedded in the third via hole and the pad trench by a method similar to that in the cases of the first and second copper wires, thereby forming the bonding pad electrically connected with the second copper wire.
However, the bonding pad is generally in the form of a rectangle (100 μm square, for example) having a relatively large area. If each pattern of the copper wires includes a pattern of the same shape opposite to the bonding pad, therefore, this pattern also has a relatively large area, similarly to the bonding pad. When copper films not embedded in the respective wiring trenches are polished by the CMP treatment, therefore, the surfaces of the copper wires are not planarized but easily indented by dishing. Particularly when a multilevel interconnection structure is formed by laminating a plurality of wiring layers, such dishing is caused in each of the wiring layers, leading to a remarkable indentation in the upper layer. This may result in various inconveniences such as defective resolution in photolithography and a short circuit between the respective wiring layers.